You can download or view the conference program here. Please note that the program might subject to change.
A shorter time schedule can be found here.
Demystifying Machine Learning for Signal and Power Integrity Applications
During last years Machine Learning (ML) approaches have been successfully applied to several realistic scenarios belonging to different research fields, including Signal Integrity (SI) & Power Integrity (PI) applications. The aim of this tutorial is twofold. On one hand, it will cover some of the basic principles of ML regression techniques. Key concepts such as: the learning paradigm, overfitting/underfitting, regularization, the “kernel trick” will be presented in an intuitive way with the help of illustrative examples. On the other hand, the second part of the tutorial will investigate the effectiveness and the strength of ML techniques for the optimization and the uncertainty quantification in real and advanced SI/PI applications. Several case studies will be presented to compare the performances of ML technique with respect to well-established state-of-the-art approaches.
Riccardo Trinchero received the M.Sc. and the Ph.D. degrees in Electronics and Communication Engineering from Politecnico di Torino, Torino, Italy, in 2011 and 2015, respectively. He is currently an Assistant Professor within the EMC Group with the Department of Electronics and Telecommunications at the Politecnico di Torino. His research interests include the analysis of switching DC-DC converters, machine learning and statistical simulation of circuits and systems.
Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML) and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center. He formerly held the positions of Founding Director, Center for Co-Design of Chip, Package, System (C3PS), Joseph M. Pettit Professor in Electronics in ECE, and Deputy Director of the Packaging Research Center (NSF ERC), GT. Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 500+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.
Future Trends on Interconnects for High End Servers
The talk will give an overview on industry trends with respect to packaging technologies and interconnects. It will start with an overview on the development of chip technology and the resulting challenges on chip-to-chip interconnects. The trend of high speed IOs in high end servers will be shown and design impact examples will be given. Different options for system integration will be explained. The co-optimization of chip, package and overall system aspects will get increased importance in the future. This optimization does lead to different solutions with respect to single-chip modules, multi-chip modules or other hybrid integration technologies depending on architecture and other boundary conditions. The tremendous increase on signal speed is changing the traditional board and card design. Moving to PAM4 the small vertical eye openings will not tolerate any larger crosstalk sources in the design like coupling from through vias or impedance mismatches caused by connectors. This is driving changes and new requirements for signal and power integrity including their design tools.
Hubert Harrer is a Senior Technical Staff Member (STSM) working in the IBM Systems Group. He received his Dipl.-Ing. degree in 1989 and his Ph.D. degree in 1992 from the Technical University of Munich. In 1993 he received a DFG (Deutsche Forschungsgemeinschaft) research grant to work at the University of California at Berkeley in the paradigm of Cellular Neural Networks.
Since 1994 he has worked for IBM in the Boeblingen Packaging Department. In 1999 he was on international assignment at IBM Poughkeepsie, New York. He is the technical lead for IBM z electronic packaging integration. This includes the systems z900, z990, z9, z10, z196, EC12, z13, z14 and z15 mainframe computers. His technical interests focus on system architecture and design, packaging technology, high frequency designs and electrical analysis for first and second level packaging. He has published multiple papers and patents on packaging.