Tutorials
Demystifying Machine Learning for Signal and Power Integrity Applications
Abstract
During last years Machine Learning (ML) approaches have been successfully applied to several realistic scenarios belonging to different research fields, including Signal Integrity (SI) & Power Integrity (PI) applications. The aim of this tutorial is twofold. On one hand, it will cover some of the basic principles of ML regression techniques. Key concepts such as: the learning paradigm, overfitting/underfitting, regularization, the “kernel trick” will be presented in an intuitive way with the help of illustrative examples. On the other hand, the second part of the tutorial will investigate the effectiveness and the strength of ML techniques for the optimization and the uncertainty quantification in real and advanced SI/PI applications. Several case studies will be presented to compare the performances of ML technique with respect to well-established state-of-the-art approaches.
Biography
Riccardo Trinchero received the M.Sc. and the Ph.D. degrees in Electronics and Communication Engineering from Politecnico di Torino, Torino, Italy, in 2011 and 2015, respectively. He is currently an Assistant Professor within the EMC Group with the Department of Electronics and Telecommunications at the Politecnico di Torino. His research interests include the analysis of switching DC-DC converters, machine learning and statistical simulation of circuits and systems.
Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML) and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center. He formerly held the positions of Founding Director, Center for Co-Design of Chip, Package, System (C3PS), Joseph M. Pettit Professor in Electronics in ECE, and Deputy Director of the Packaging Research Center (NSF ERC), GT. Prior to joining GT, he was with IBM working on packaging for supercomputers.
He is the author of 500+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.
Preliminary Conference Program
High Speed Design and Signal Integrity Analysis
The Sensitivity of ENRZ to skew – In Comparison to NRZ, PAM3, and PAM4 – S. S. Chen, Z. Xu | |
High Density RRAM Arrays With Improved Thermal and Signal Integrity – K. Lahbacha, H. Belgacem, W. Dghais, F.Zayer, A. Maffucci | |
Error Propagation in Channel Operating Margin L. Bai |
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Intra-Pair Skew Metric, EIPS (Effective Intra-Pair Skew) S.-J. Moon, J., X. Zhang, C.-P. Kao, B. Lee, H. Dsilva, J.-R. Guo |
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Analysis of Differential Crosstalk and Transmission for Via Arrays in Low Temperature Cofired Ceramics Ö. F. Yildiz, N. Pathé, M. Bochard, C. Yang, C. Schuster |
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Generalized ccICN (component contribution Integrated Crosstalk Noise) for PAM-N S.-J. Moon, Z. Wu, M. Mazumder |
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Distributed PDN Modeling Approach for Accurate Jitter Estimation in High Speed NAND Flash Memory S. Mobin, P. Balachander, A. Sharma, J. Lee, V. Ramachandra, C. D. Nguyen |
Design Methodology for Signal and Power Integrity Analysis
Bayesian Optimization of Hyperparameters in Kernel-Based Delay Rational Models F. Treviso, R. Trinchero, F. G. Canavero |
Fast and Stable Transient Simulation of Nonlinear Circuits using the Numerical Inversion of the Laplace Transform B. Bandali, E. Gad, M. Nakhla |
A Novel Methodology for Variability Analysis of CMOS Circuits using Simulated Annealing – A. Chordia, S. Hemaram, J. N. Tripathi |
A Compact and Broadband On-Chip Delay Line Design Based on the Bridged T-Coil – S. R. Mahendraand, A. Weisshaar |
Design and analysis method for power converters with GaN devices in parallel – R. Franchino, R. Mitova |
Advanced Interconnect Technologies
Electrothermal Modeling and Characterization of Graphene-Based Thin Strips A. Maffucci, L. Ferrigno, S. Sibilia, F. Bertocchi, S. Chiodini, F. Cristiano, G. Giovinco |
Investigation of an integrated directional coupler manufactured by a field-assisted diffusion process – D. Uebach, T. Kühler and E. Griese |
De-mystifying the impact of Intra-pair Skew on high-speed SerDes Interconnect H. Dsilva, S. McMorrow, A. Gregory,S. Krooswyk, R. Mellitz, B. Lee |
Design Support by Machine Learning and Artificial Intelligence
Comparative study of Machine Learning methods for variability analysis in High-speed link – T. Nguyen, B. Shi, J. Schutt-Aine |
Machine Learning-Based Verilog-A Modeling for Power Distribution Network of On-Die Regulator – M. Chang, S. Kao, S. Chu, B. Hsu, M. Ciou, K. Chung, R. Ho |
ANN Hyperparameter Optimization by Genetic Algorithms for Via Interconnect Classification – A. Sánchez-Masís, A. Carmona-Cruz, M. Schierholz, X. Duan, K. Roy, C. Yang, R. Rimolo-Donadio, C. Schuster |
Macro-Modeling
A Multivariate Adaptive Sampling Scheme for Passivity Characterization of Parameterized Macromodels M. De Stefano, S. Grivet-Talocia |
A Tunable Macro-Modeling Method for Signal Transition in mm-Wave Flip-Chip Technology P. Namaki, M.-R. Nezhad-Ahmadi, N. Masoumi, S. Safavi-Naeini |
Macro-modeling of Switching Noise for Buck Converter using Parameter Fitting Method A. Huang, S. PK, S. Singh, B. Mutnury, J. Drewniak, C. Hwang |
Measurement and Characterization
Non-destructive PCB Substrate Height Extraction with Multi-Measurement Technique T. Wang Lee, F. de Paulis, M. Resso, M. Piket-May, E. Bogatin |
Impact of Chuck Boundary Conditions on Wideband On-Wafer Measurements G. N. Phung, U. Arz |
Stochastic Analysis and Uncertain Quantification
A Nonparametric Surrogate Model for Stochastic Crosstalk Analysis Including Confidence Bounds – P. Manfredi, R. Trinchero |
Stochastic Analysis Method for Tree-Type PDNs on Mixed-Signal PCB M. Mehri |
A Multi-Fidelity Polynomial Chaos Approach for Uncertainty Quantification of MWCNT Interconnect Networks in the Presence of Imperfect Contacts S. Guglani, KM Dimple, B. K. Kaushik, S. Roy, R. Sharma |
Uncertainty Quantification of Memristor Crossbar Array for Vector Matrix Multiplication R. Kumar, A. Chordi, A. James, J. N. Tripathi |